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Design Engineer Trainee
Qloq Technologies
B Tech/M Tech ECE
Key Skills:VLSI
Roles & Responsibilities:
Understanding or prior experience with Industry standard protocols like USB, SPI, SATA, Ethernet, DisplayPort, SRIO etc is a definite plus
BE/B.Tech, MS
Fulltime Internship10000 Monthly
01-07-2016 To 30-09-2016
Last Date To Apply:30-09-2016
Job Description About Employer

Develop verification testbench components for chip/module level using System Verilog, C & Perl
Use high level language concepts (Object oriented, UVM/OVM/VMM etc) to develop extendable environment.
Define and execute detailed verification plan from spec working with architects, designers, system engineers.
Write tests, automate regression scripts and regression environment.
Incorporate code-coverage, functional coverage, assertions, cover-groups etc to achieve 100% verification completeness prior to tapeout.
Debug tests, run gate level simulations at unit/sdf delays
Develop automated/scripted design flows for the above mentioned development processes
Participate in FPGA/silicon debug and analysis
Excellent debugging skills in both SW and ASIC hardware
Must be proficient in Verilog (System Verilog preferred).
Proficiency in scripting language like Perl, Tcl/Tk, Shell is a definite plus.
Experience with simulators like ncVerilog (Incisive), VCS and QuestaSim.
Good understanding of latest formal verification techniques, assertions, OOP etc is a plus.

Other Requirements:

At Qloq Technologies, we develop high quality Semiconductor Design and Verification IPís (Intellectual property), to be used directly into a SoC/Custom Design. We are currently working on some of the interesting Protocols/Subsystem, which are unique in terms of implementation and performance. Besides working on interesting things for industry, we also help out students and new college graduates, Junior engineers on training them with the latest languages and tools.
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