Develop verification testbench components for chip/module level using System Verilog, C & Perl
Use high level language concepts (Object oriented, UVM/OVM/VMM etc) to develop extendable environment.
Define and execute detailed verification plan from spec working with architects, designers, system engineers.
Write tests, automate regression scripts and regression environment.
Incorporate code-coverage, functional coverage, assertions, cover-groups etc to achieve 100% verification completeness prior to tapeout.
Debug tests, run gate level simulations at unit/sdf delays
Develop automated/scripted design flows for the above mentioned development processes
Participate in FPGA/silicon debug and analysis
Excellent debugging skills in both SW and ASIC hardware
Must be proficient in Verilog (System Verilog preferred).
Proficiency in scripting language like Perl, Tcl/Tk, Shell is a definite plus.
Experience with simulators like ncVerilog (Incisive), VCS and QuestaSim.
Good understanding of latest formal verification techniques, assertions, OOP etc is a plus.